Does it matter if the stopping block for verifying an EVM is truthful is the IPR is for ICs/ board level design? Who cares if the IPR block is due to the fan design or of the IPR of how smoothly they cut the board or the colour of a capacitor.Raja Bose wrote: You are mixing up IPR for the board level design with IPR for the ICs. In context of Pranav's post I was referring to IPR for the ICs which have been around for a large number of years (you probably have 6-12 of them around you right now). The IPR for the ICs is not owned by ECIL/BEL and is licensed to them by Microchip etc.. I do not condone the ham fisted approach by ECIL/BEL. In fact, on this thread it was suggested they should simply make the people who wanted to hack the EVM sign an NDA (non-disclosure agreement) and then provide them access - this is a standard practice the world over. Unfortunately such paranoia just provides fodder for the conspiracy theorists.
The issue is the EC is blocking ANY meaning full test of the EVM citing IPR/nonsense.
They can have all the IPR they want, but not when it has even a single possible attack through that.
You/ this thread might have suggested 10,000 proper ways. The issue is how many is EC publicly following? According to my reckoning of proper public procedures on last count- exactly 0.
What you/ Dileep/ Rahul Mehta/me say doesnt matter. The only thing that matters is what EC is doing?
You might say "any engineer worth his salt" would follow XYZ procedures. But when I ask Do you EXACTLY know the exact engineer working there is worth whosever salt, all I see instead of yes/no and proofs but answers skipping them with long monologues of some technological marvels.
is it possible that they withdrew (note they withdrew not rejected) for the exact same reason as mentioned in bold. Now they do not need to make anything public and seemingly not in a rush to do it in the forseeable future.Yes, they will be rejected because there is nothing novel about the Indian EVM's board level design which has not already been covered by prior art. I am not sure how that seems relevant to you in any way in context of the security aspects of the EVM. Also, do remember that applying for a patent implies it will be made public within 18 months so if they had anything to hide in the design itself, they would not have applied for a patent in the first place and would just classify it as a trade secret (common practice in industry esp. in defence).